We provide here the handouts of the course in Adobe PDF.

Note - this material is no substitute for the lecture itself nor for own notes.
Handouts Last updated Source code of the examples (click on the name for text-only/download or on the extension for syntax coloured output)
Introduction to digital design (2013.06.02)
Designing with VHDL (2013.06.06)          a2of3.vhd       fadd_top.vhd           xor3.vhd       tristate.vhd          bidir.vhd          mux31.vhd      mux21nbit.vhd          mux41.vhd      gate_vect.vhd          prior.vhd        mux4reg.vhd          demux.vhd          adder.vhd         mypack.vhd gate_vect_ovld.vhd         barrel.vhd        numones.vhd        dff_lat.vhd  dff_set_reset.vhd      dff_aload.vhd  shift_reg_var.vhd        counter.vhd      shift_reg.vhd shift_reg_full.vhd       bin2gray.vhd       gray2bin.vhd       gray_cnt.vhd     filt_short.vhd      filt_long.vhd          sort2.vhd          sort4.vhd         sort4b.vhd        sort4mm.vhd         sort4c.vhd          sort8.vhd       reg_file.vhd      state_2ph.vhd         sort4c.cpp
Simulation with VHDL (2009.06.05)    reg_file_tb.vhd       Makefile.func
Introduction to DSP (2009.06.16)      sin_lut90.vhd        sin_lut.vhd         cordic.vhd        mov_int.vhd           tail.vhd      iir_relax.vhd        fir5tap.vhd        sin_lut.cpp         cordic.cpp
The real hardware (2013.06.07)       Makefile.altera       Makefile.xilinx
IP cores (2013.06.07)          ssram.vhd        dp_sram.vhd     dc_dp_sram.vhd        sc_fifo.vhd     resync_sdr.vhd
Examples (2009.06.30)
Introduction to Verilog (2009.07.07)           demo.v          parity3.v              top.v            gates.v      comb_always.v            bidir.v         tristate.v       mux21_nbit.v          top_mux.v     prior_assign.v    prior_if_else.v      prior_casex.v       gate_array.v   gate_array_for.v   mux21_nbit_wor.v        wired_and.v            mux31.v        demux2to4.v            demux.v            adder.v         barrel_v.v             dffe.v         dffs_r_e.v          dff_s_r.v         udp_test.v          latches.v      mux31_latch.v          counter.v        shift_reg.v    shift_reg_var.v   shift_reg_var_tb.v          regfile.v       regfile_tb.v        psrg_func.v         psrg_gen.v      filt_shortv.v       filt_longv.v       state_2phv.v  
Logic Box (2013.06.24) DL709_template.vhd       top_core.vhd             LB.zip       inst_win.zip       inst_lnx.zip readme_lbox_demo.txt
Control questions (2009.07.02)