LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
entity tail is
generic(Nd : Integer := 8; -- data width
clp : Boolean := true;
Nc : Integer := 6); -- bits in c
port (
clk : in std_logic;
clr : in std_logic;
x : in std_logic_vector(Nd-1 downto 0); -- input data
c : in std_logic_vector(Nc-1 downto 0); -- coeff = c/2**Nc
y : out std_logic_vector(Nd-1 downto 0)); -- output
end tail;
architecture a of tail is
signal diffe : std_logic_vector(Nd downto 0);
signal prod : std_logic_vector(Nd+Nc-1 downto 0);
signal xold_c : std_logic_vector(Nd -1 downto 0);
begin
diffe <= ('0' & x) - ('0' & xold_c);
y <= diffe(y'range) when not clp or diffe(Nd)='0' else (others => '0');
prod <= x * c;
process(clk)
begin
if rising_edge(clk) then
if clr='1' then
xold_c <= (others => '0');
else
xold_c <= prod(Nd+Nc-1 downto Nc);
end if;
end if;
end process;
end;