LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; entity fir5tap is generic(N : Positive := 8); port( clk : in std_logic; din : in std_logic_vector(N-1 downto 0); dout : out std_logic_vector(N-1 downto 0) ); end fir5tap; architecture a of fir5tap is type taps_type is array(0 to 4) of std_logic_vector(N+3 downto 0); signal taps : taps_type; begin process(clk) begin if rising_edge(clk) then taps(0) <= "0000" & din; -- y0 taps(1) <= taps(0) + ("00" & din & "00"); -- + 4*y1 taps(2) <= taps(1) + ( ("00" & din & "00") + ("000" & din & '0') ); -- + 6*y2 taps(3) <= taps(2) + ("00" & din & "00"); -- + 4*y3 taps(4) <= taps(3) + ("0000" & din); -- + y4 end if; end process; dout <= taps(4)(N+3 downto 4); end;