############################# # Project specific settings # ############################# # The top level design name design=cnt3 # The source file(s), the last is the top src_files=../SRC/my_and.vhd ../SRC/my_or.vhd ../SRC/cnt2bit.vhd ../SRC/$(design).vhd # The testbench file(s) testbench=./SRC/clk_gen.vhd ./SRC/$(design)_tb.vhd # Compile the sources for functional simulation functional: $(src_files) vlib $@ vcom -quiet -93 -work $@ $(src_files) # Functional Simulation simfun: $(testbench) functional vmap libdut functional rm -rf work vlib work vcom -quiet -93 -work work $(testbench) vsim 'work.$(design)_tb' -t 1ns -do 'wave_fun.do' # Clean all library directories clean: rm -rf functional work modelsim.ini transcript vsim.wlf .PHONY: simfun clean