library ieee;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
entity reg_file is
generic (Na : Positive := 3;
Nd : positive := 16);
port(
clk : in std_logic;
rst_n : in std_logic;
we : in std_logic;
waddr : in std_logic_vector(Na-1 downto 0);
din : in std_logic_vector(Nd-1 downto 0);
raddra : in std_logic_vector(Na-1 downto 0);
raddrb : in std_logic_vector(Na-1 downto 0);
rdata : out std_logic_vector(Nd-1 downto 0);
rdatb : out std_logic_vector(Nd-1 downto 0) );
end reg_file;
architecture a of reg_file is
--subtype reg_data is std_logic_vector(Nd-1 downto 0);
--type rf_data_array is array(0 to 2**Na-1) of reg_data;
type rf_data_array is array(0 to 2**Na-1) of std_logic_vector(Nd-1 downto 0);
signal rf_data : rf_data_array;
signal we_i : std_logic_vector(rf_data_array'range);
begin
-- decoder with enable
process(waddr, we)
begin
we_i <= (others => '0');
we_i(conv_integer(waddr)) <= we;
end process;
-- the registers
ri: for i in rf_data_array'range generate
process(clk, rst_n)
begin
if rst_n = '0' then rf_data(i) <= (others => '0');
elsif clk'event and clk='1' then
if we_i(i) = '1' then
rf_data(i) <= din;
end if;
end if;
end process;
end generate;
-- the two output mux
rdata <= rf_data(conv_integer(raddra));
rdatb <= rf_data(conv_integer(raddrb));
end;