`timescale 1 ns / 1 ns module shift_reg(clk, load, rst_n, din, serin, shift, dout, serout); parameter time del = 10; parameter N = 4; input clk, load, rst_n, serin, shift; input [N-1:0] din; output serout; output [N-1:0] dout; reg [N-1:0] q; always @(posedge clk or negedge rst_n) begin if (rst_n == 0) q <= 0; else if (load == 1) q <= din; else if (shift == 1) q <= {q[N-2:0], serin}; end assign # del serout = q[N-1]; assign # del dout = q; endmodule