Exported from Notepad++

-- $Id: DL709.vhd 346 2013-06-20 15:46:03Z angelov $: -- =============================================================================== -- MODULE DL709 -- ------------------------------------------------------------------------------- -- Top entity for DL709 -- =============================================================================== library IEEE; use IEEE.std_LOGIC_1164.ALL; use work.LogicBox_pkg.all; use work.svn_extract.all; entity DL709 is Port ( CLK : in std_logic; RES_n : in std_logic; LED_Back : out std_logic; -- put here the signals to the SUxxx modules -- SU_BEGIN <- please don't delete or modify this comment! -- SU_END -- end of the SUxxx section -- FX2 FXClk : out std_logic; FXAddr : out std_logic_vector( 1 downto 0); FXData : inout std_logic_vector( 7 downto 0); FXRD_n : out std_logic; FXWR_n : out std_logic; FXSLOE_n : out std_logic; FXEmpty : in std_logic; FXFull : in std_logic; FXPEnd_n : out std_logic); end DL709; architecture struct of DL709 is component usb2cbus_fx2 is Generic (IDNr : std_logic_vector(31 downto 0) := (others => '1'); SVN_ID : std_logic_vector(31 downto 0) := (others => '1'); CRDY_CYC : natural := 1); Port ( CLK : in std_logic; RES_n : in std_logic; Tick1ms : out std_logic; Tick20ms : out std_logic; LED_Back : out std_logic; -- USB FXClk : out std_logic; FXAddr : out std_logic_vector( 1 downto 0); -- Adresse FIFO FXData : inout std_logic_vector( 7 downto 0); -- Datenbus FIFO FXWR_n : out std_logic; -- Write Strobe FXRD_n : out std_logic; -- Read Strobe FXSLOE_n : out std_logic; FXEmpty : in std_logic; -- Receive FXEmpty (Read when Low) FXFull : in std_logic; -- Transmit FXFull (Write when Low) FXPEnd_n : out std_logic; -- Transmit Package End Reset : out std_logic; status : out std_logic_vector(15 downto 0); -- DMA config & handshaking DMA_ena : out std_logic; -- DMA enabled DMA_ack : out std_logic; -- DMA acknoledge DMA_req : in std_logic; -- request, activate only when DMA_ena=1, deactivate after ack DMA_Nwords : in std_logic_vector(15 downto 0); -- Number of words DMA_Addr : in std_logic_vector(31 downto 0); -- start address DMA_dsize : in std_logic_vector( 1 downto 0); -- 0..3 for 1..4 bytes DMA_Ainc : in std_logic; -- auto increment of the address -- CBus CReset : out std_logic; CAddr : out std_logic_vector(31 downto 0); CWR : out std_logic; CRD : out std_logic; CDIn : in std_logic_vector(31 downto 0); CDOut : out std_logic_vector(31 downto 0); CRdy : in std_logic); end component; component top_core is Generic(ClkMHz : integer := 100); Port ( CLK : in std_logic; Reset : in std_logic; -- put here the signals to the SUxxx modules -- SU_BEGIN <- please don't delete or modify this comment! -- SU_END -- end of the SUxxx section Tick1ms : in std_logic; Tick20ms : in std_logic; -- DMA config & handshaking DMA_ena : in std_logic; -- DMA enabled DMA_ack : in std_logic; -- DMA acknoledge DMA_req : out std_logic; -- request, activate only when DMA_ena=1, deactivate after ack DMA_Nwords : out std_logic_vector(15 downto 0); -- Number of words DMA_Addr : out std_logic_vector(31 downto 0); -- start address DMA_dsize : out std_logic_vector( 1 downto 0); -- 0..3 for 1..4 bytes DMA_Ainc : out std_logic; -- auto increment of the address -- IF CAddr : in std_logic_vector(31 downto 0); CWR : in std_logic; CRD : in std_logic; CDIn : in std_logic_vector(31 downto 0); CDOut : out std_logic_vector(31 downto 0); CRdy : out std_logic); end component; ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ constant svn_rev : string := "$Rev: 346 $"; constant svn_date : string := "$Date: 2013-06-20 17:46:03 +0200 (Thu, 20 Jun 2013) $"; constant svn_id : std_logic_vector(31 downto 0) := DateSVN(revision => svn_rev, datestr => svn_date); signal CReset, CWR, CRD, CRdy : std_logic; signal CAddr,CDIn,CDOut : std_logic_vector(31 downto 0); signal Tick1ms, Tick20ms : std_logic; signal Reset : std_logic; signal DMA_ena : std_logic; -- DMA enabled signal DMA_ack : std_logic; -- DMA acknoledge signal DMA_req : std_logic; -- request, activate only when DMA_ena=1, deactivate after ack signal DMA_Nwords : std_logic_vector(15 downto 0); -- Number of words signal DMA_Addr : std_logic_vector(31 downto 0); -- start address signal DMA_dsize : std_logic_vector( 1 downto 0); -- 0..3 for 1..4 bytes signal DMA_Ainc : std_logic; -- auto increment of the address begin --======================================================================== ------------------------------------------------------------------------------------ USB_CTRL: usb2cbus_fx2 Generic MAP( IDNr => DateTimeVID, SVN_ID => svn_id) Port Map( CLK => CLK, RES_n => RES_n, Tick1ms => Tick1ms, Tick20ms => Tick20ms, LED_Back => LED_Back, -- FX2 USB FXClk => FXClk, FXAddr => FXAddr, FXData => FXData, FXWR_n => FXWR_n, FXRD_n => FXRD_n, FXSLOE_n => FXSLOE_n, FXEmpty => FXEmpty, FXFull => FXFull, FXPEnd_n => FXPEnd_n, Reset => Reset, status => open, -- DMA config & handshaking DMA_ena => DMA_ena, DMA_ack => DMA_ack, DMA_req => DMA_req, DMA_Nwords => DMA_Nwords, DMA_Addr => DMA_Addr, DMA_dsize => DMA_dsize, DMA_Ainc => DMA_Ainc, -- CBUS CReset => CReset, CAddr => CAddr, CWR => CWR, CRD => CRD, CRdy => CRdy, CDIn => CDIn, CDOut => CDOut); ------------------------------------------------------------------------------------ LP: top_core Generic Map( ClkMHz => ClkMHz) Port Map( CLK => CLK, Reset => CReset, -- put here the mapping of the signals to the SUxxx modules -- SU_MAP_BEGIN <- please don't delete or modify this comment! -- SU_MAP_END -- end of the SUxxx section Tick1ms => Tick1ms, Tick20ms => Tick20ms, -- DMA config & handshaking DMA_ena => DMA_ena, DMA_ack => DMA_ack, DMA_req => DMA_req, DMA_Nwords => DMA_Nwords, DMA_Addr => DMA_Addr, DMA_dsize => DMA_dsize, DMA_Ainc => DMA_Ainc, -- IF CAddr => CAddr, CWR => CWR, CRD => CRD, CDIn => CDOut, CDOut => CDIn, CRdy => CRdy); end;