module prior_if_else(irq, valid, irq_no); input [3:0] irq; output valid; output [1:0] irq_no; reg [1:0] irq_no; reg valid; always @(irq) begin irq_no <= 2'bxx; valid <= 1'b0; if (irq[3]==1'b1) begin irq_no <= 2'd3; valid <= 1'b1; end else if (irq[2]==1'b1) begin irq_no <= 2'd2; valid <= 1'b1; end else if (irq[1]==1'b1) begin irq_no <= 2'd1; valid <= 1'b1; end else if (irq[0]==1'b1) begin irq_no <= 2'd0; valid <= 1'b1; end end endmodule