LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.all; entity counter is generic (N : Natural := 8; t_co : Time := 10 ns); port ( clk : in std_logic; rst_n : in std_logic; sload : in std_logic; cnten : in std_logic; d : in std_logic_vector(N-1 downto 0); co : out std_logic; q : out std_logic_vector(N-1 downto 0) ); end counter; architecture a of counter is signal q_i : std_logic_vector(q'range); constant full : std_logic_vector(q'range) := (others => '1'); begin process(clk) begin if clk'event and clk='1' then if rst_n = '0' then q_i <= (others => '0'); elsif sload = '1' then q_i <= d; elsif cnten = '1' then q_i <= q_i + 1; end if; end if; end process; q <= q_i after t_co; co <= '1' after t_co when q_i = full and sload = '0' and cnten = '1' else '0' after t_co; end;