module top_mux(I0, I1, I2, I3, SEL, Y); parameter Width = 2; input [Width-1:0] I0, I1, I2, I3; input [1:0] SEL; output [Width-1:0] Y; wire [Width-1:0] Y01, Y23; mux21_nbit #(Width) u1 (.I0(I0), .I1(I1), .SEL(SEL[0]), .Y(Y01)); mux21_nbit #(Width) u2 (.I0(I2), .I1(I3), .SEL(SEL[0]), .Y(Y23)); //mux21_nbit #(Width) u3 (.I0(Y01), .I1(Y23), .SEL(SEL[1]), .Y(Y)); mux21_nbit u3 (.I0(Y01), .I1(Y23), .SEL(SEL[1]), .Y(Y)); defparam u3.N=Width; endmodule