LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity dff_lat is
port (
clk : in std_logic;
rst : in std_logic;
d : in std_logic;
qd : out std_logic;
ql : out std_logic);
end dff_lat;
architecture a of dff_lat is
signal qi : std_logic;
begin
-- DFF
process(clk, rst)
begin
if rst = '1' then
qd <= '0';
elsif clk'event and clk='1' then
qd <= d;
end if;
end process;
-- Latch
process(clk, d, rst)
begin
if rst = '1' then
ql <= '0';
elsif clk='1' then
ql <= d;
end if;
end process;
end;