LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity gate_vect is generic (N : Natural := 4); port ( a : in std_logic_vector(N-1 downto 0); g : in std_logic; y : out std_logic_vector(N-1 downto 0) ); end gate_vect; architecture a of gate_vect is -- overload "and" for the case bit AND bit_vector function "and" (L: std_logic; R: std_logic_vector) return std_logic_vector is variable tmp : std_logic_vector(R'range); begin for i in R'range loop tmp(i) := R(i) and L; end loop; return tmp; end; -- overload "and" for the case bit_vector AND bit function "and" (L: std_logic_vector; R: std_logic) return std_logic_vector is begin return R and L; end; begin -- use only one of them! y <= g and a; y <= a and g; end;