LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity gray2bin is
generic (N : Natural := 2);
port (
gray : in std_logic_vector(N-1 downto 0);
bin : out std_logic_vector(N-1 downto 0) );
end gray2bin;
architecture a of gray2bin is
signal bin_i : std_logic_vector(gray'range);
begin
bin_i(N-1) <= gray(N-1);
linc: for i in N-2 downto 0 generate
bin_i(i) <= gray(i) xor bin_i(i+1);
end generate;
bin <= bin_i;
end;