library ieee; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; entity dc_dp_sram is generic (Na : Positive := 8; Nd : positive := 16); port( wclk : in std_logic; rclk : in std_logic; we : in std_logic; waddr : in std_logic_vector(Na-1 downto 0); raddr : in std_logic_vector(Na-1 downto 0); din : in std_logic_vector(Nd-1 downto 0); dout : out std_logic_vector(Nd-1 downto 0) ); end dc_dp_sram; architecture a of dc_dp_sram is type t_mem_data is array(0 to 2**waddr'length - 1) of std_logic_vector(dout'range); signal mem_data : t_mem_data; signal raddri : integer range 0 to 2**raddr'length - 1; signal waddri : integer range 0 to 2**waddr'length - 1; begin waddri <= conv_integer(waddr); ram: process(wclk) begin if wclk'event and wclk='1' then if we = '1' then mem_data(waddri) <= din; end if; end if; end process; process(rclk) begin if rclk'event and rclk='1' then raddri <= conv_integer(raddr); end if; end process; dout <= mem_data(raddri) after 5 ns; end;