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Master Arbeiten
| Development of new pixel detectors based on the High-Voltage MAPS Technology | André Schöning |
| Our group is developing a new pixel detectors based on the High-Voltage MAPS (monolithic active pixel detector) technology. This new technology is superior in many respects compared to standard hybrid silicon detectors. It will be used for the new Mu3e experiment and is also considered for the LHC-High Luminosity upgrade of the ATLAS experiment. We offer several bachelor and master theses in this area. For more information contact A.Schoening. | |
| Experimentelle und theoretische Tests der Quantenmechanik bei niedrigsten Energien | Maarten DeKieviet |
Das in Heidelberg entwickelte 3He-Atomstrahl-Spinecho-Spektrometer ermöglicht das Vermessen kleinster Energieänderungen (~100 peV) in der Wechselwirkung zwischen Atomen und Felder oder Materie. Das Experiment ist in seiner Form weltweit einzigartig und erforscht derzeit:
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| New Physics using Geometric Algebra | Maarten DeKieviet |
| Instead of having special mathematics for all the different fields of physics, Geometric Algebra (GA) supplies a unified and unifying mathematical language for the whole of physics. It not only allows for a geometric interpretation of the constituent elements, it uncovers hidden connections between the otherwise seemingly unrelated mathematical descriptions. Why hasnt anyone told me that before? is a regularly heard, awing reaction of students being exposed to this language for the first time. We are currently searching for discrepancies with and extensions of the regular mathematical approach, both theoretically and experimentally. These are exciting times, come and join us! | |
| Development of a test bench for the Pattern Recognition Engine | Sebastian Dittmeier, |
| The High-Luminosity LHC will be the most challenging environment to perform online particle track reconstruction in the world. The ATLAS experiment addresses this challenge using pattern recognition fully implemented in hardware using several thousands of custom-designed Associative Memory ASICs (Application-Specific Integrated Circuit), which have an individual comparison power of 3.75 Petabyte per second per chip. We want to build a test bench for the printed circuit board, the so-called Pattern Recognition Mezzanine, which hosts 20 of these ASICs and an extremely powerful FPGA (Field-Programmable Gate Array). We offer bachelor and master theses. If interested please contact S.Dittmeier or A.Schöning. | |
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