Ruprecht Karls Universität Heidelberg
Bild Institut
Physikalisches Institut
Im Neuenheimer Feld 226
69120 Heidelberg

Tel: +49 6221-54 19600
Fax: +49 6221-54 19540
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Stellenangebote - Bachelorarbeiten


Development of a new pixel detector in High Voltage-MAPS technologyAndré Schöning
Our group is developing a new pixel detectors based on the High-Voltage MAPS (monolithic active pixel detector) technology. This new technology is in many respects superior compared to standard hybrid silicon detectors. It will be used for the new Mu3e experiment and is considered for the LHC-High Luminosity Upgrades. We offer several bachelor and master theses in this area. This project also qualifies as Projektpraktikum.

Development of a test bench for the Pattern Recognition EngineSebastian Dittmeier,
The High-Luminosity LHC will be the most challenging environment to perform online particle track reconstruction in the world. The ATLAS experiment addresses this challenge using pattern recognition fully implemented in hardware using several thousands of custom-designed Associative Memory ASICs (Application-Specific Integrated Circuit), which have an individual comparison power of 3.75 Petabyte per second per chip. We want to build a test bench for the printed circuit board, the so-called Pattern Recognition Mezzanine, which hosts 20 of these ASICs and an extremely powerful FPGA (Field-Programmable Gate Array). We offer bachelor and master theses. If interested please contact S.Dittmeier or A.Schöning.

Development of a new pixel sensor readout systemSebastian Dittmeier,
For the Mu3e experiment, we are developing and characterizing High-Voltage monolithic active pixel sensors. We have developed a new FPGA readout board for the pixel sensors. Due to the generic nature of the readout board, it can also be used as a standalone readout system for lab studies of single sensors or test beam measurements operating a multi-layer beam telescope. We are looking for interested bachelor or master students to implement and test the interface, e.g. via Ethernet, between the FPGA and the data acquisition PC. This project allows for hands-on experience on the development of hard-, firm- and/or software.

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