{Radiation issues} The components used on the DCS-board have to cope with a certain radiation level. Jet Propulsion Laboratory radiation test database.

{TTCrx} The clock distribution is part of the DCS-board functionality. CERN provides the experiments with an ASIC called TTCrx. This chip is part of the TTC (Timing Trigger and Control) system of the LHC experiments. In order to integrate the timing and clock issues each DCS board has one TTCrx chip. Some measurements on the timing jitter on this chip are reported on a CMS homepage. The measurement has to be compared to an older measurement. Even with this improved jitter the LHCb outer tracker group will use a QPLL for further improvements. The QPLL ASIC is a Phase-Locked Loop based on a voltage controlled Quartz crystal oscillator (VCXO). Further information on the QPLL-Homepage.
I initiated a TTCrx collaboration with the LHCb outer tracker group @ Heidelberg. (26.11.2002)

{short meeting notes (Sasco/Altera)} Participants: DG, HH, VA, TA, and MS. Results:
The focus of investigation was pointed to the STRATIX device (CRC check sum to check the device configuration). Concerning the JTAG FLASH recovery new informations are available but not public ----> email me. No radiation tests are done by ALTERA.

{short meeting notes} Participants: DG, HH, VP, IR and MS. Results:
This was a very short status-report of the developement of the DCS-board. The actual versions of the DCS Specification and Working Document will be the stated link for the future. The hardware-link for the optical link of the TTCrx chip was shortly discussed. First implementations of the JTAG recovery procedure were discussed.
New discussion date: 21/11/2002 9:00 c.t. Turmzimmer (11/15/2002)

{short meeting notes} Participants: DG, HH, VP, IR and MS. Results:
In order to test the recovery scheme of the flash memory and/or the FPGA program via the JTAG chain a test-board with the EPXA4 has to be used. One with the EPXA1 is ordered and will be delivered in 2-3 weeks. The Clock is delivered from the DCS board via two differential clock-lines (four traces on the board/four pins from the DIMM connector). Starting from the half-chamber-merger the clock-signals are propagated to the board-merger followed by the row-merger to the individual MCMs. This scheme gives the maximum trace length of about 55cm to the next chip (one of those half-chamber merger). The pre-trigger will be distributed in the same way using two differential lines. As base of the discussion the preprepreliminary version of the Pflichtenheft created by DG was used.
New discussion date: 14/11/2002 9:00 c.t. Turmzimmer (11/08/2002)
Updated version of the DCS Specification and Working Document. This website will replace from now on the older documents reffered to below. (11/14/2002)

{short meeting notes} Participants: DG, HH, VP, and MS. Results:
The number of connection lines through the DIMM144 connector was discussed. The updated number will be included in the document stated below. For the LVDS part 4 bidirectional chains are needed ---> 8 lines have to be taken into account. For the JTAG connection 2*5 pins to connect the 5 DCS-boards of one module plane (along the z-axis of the detector). The Voltage readings of the primary power lines have to be connected on a separate connector on the DCS-board
First implementation ideas for the flash ROM recovery procedure are discussed. The idea introduced by VP needs the JTAG chain. In order to guarantee the recovery of the flash ROM the neighboring DCS-board has to act as a JTAG master. A implementation of this scheme implies the necessity to switch from the JTAG-slave mode to the master mode. A implementation of this kind needs further evaluation and testing. (Two test-boards with the ARM core FPGA....)
The question question of resetting MCM modules, which needs additional traces on the readout-board, was raised. The routing on the different readout boards (3 different versions are needed for one chamber!) roles out separate reset lines. The resetting can be done via switching the power.
The fixing of the DCS-board was shortly discussed. The DIMM connector could be modified (cutting the the normal PCB holder essentially)

New discussion date: 07/11/2002 9:00 c.t. Turmzimmer (25/10/2002)
Updated version of the DIMM connector definition. (10/28/2002)

{TRD/DCS Project} All existing work on the DCS-board and DCS in general was done by VP and is summarized on the DCS Homepage. Starting from this DG and HH are working on a layout for the DCS-board. A first proposal by them is found here. In this document the DIM 144 Connector is described.(10/23/2002)

{short meeting notes} Participants: DG, HH,short IR, VP and MS. Results:
DG will start with the digital part of the DCS-board. The large footprint of the EPXA1 should be used. Instead of starting wit the EPXA1 the EPXA4 will be implemented. The LVDS provided by the latter is easier to use. For debugging reasons there should be included as many as debugging features as possible. Namely: trace ports (from the FPGA), JTAG from the ARM Core (eventually JTAG from the FPGA part). To have the opportunity to access the data transferred from the main data merger a TTL20 data connection has to be implemented. The JTAG is eventually needed for the reconfiguration of the flash RAM if somehow destroyed.
Space requirement? We have in total 18mm for the DCS-board including everything! The dimensions of the board should not exceed 10cm times 12cm
The TDCrx part: MS has to find the recent layouts in order to implement the low jitter version as measured by CMS. (Copy and Paste, hopefully;-))
MS has to ask VL about the MCMs. Especially the voltage and temperature measurements on them!
New discussion date: 24/10/2002 9:00 c.t. Turmzimmer (18/10/2002)

{First Plans} A short discussion took place. Participants: DG, HH, partially IR,and MS. Main points/questions:
Which voltages have to be read out?
Where to place which temperature sensors?
What kind of sensors will be used?
Multiplexer on the DCS board or on the read-out board?
---> here: multiplexer on the read-out board would reduce the number of lines (pins in the connector) drastically.
New discussion date: 17/10/2002 (10/10/2002)