Summary of meeting 23.5. at KIP (V.A.,R.G.,I.R.,V.P.)
Venelin produced first version of the
Block
diagram of the slow control + TTC module. Here is the first drawing of component
layout and some notes. Here are datasheets,
footprints, and prices of components (by Tobias) . Here is the ORCAD
CAPTURE
library for components on DSC TTC board.
Definition of TTC part:
Depanding on batch TTC ASIC is produced in two packages: 15x15mm 100 BGA package (first production) or 13x13mm 144 fpBGA package . For basic timing&trigger functionality is necessary circuitry of TTCrm mezzanine module here is PCB layout and detailed scheme block scheme and PCB picture. The TTCrx design has now been improved and migrated to DMILL radiation-hard technology. In the DMILL version of the TTCrx ASIC the JTAG controller is supplemented by an I2C bus interface. This interface allows an external I2C controller to write and read all the TTCrx internal registers. An initialization PROM is no longer required for this new version, which also supports more user-defined broadcast codes and has lower trigger latency. A list of the changes which have been implemented in the DMILL TTCrx is given in "TTCrx Modifications".
Various optoelectronic receivers can be used in the TTC system. Many existing systems use a photodiode+preamplifier (Agilent HFBR-2316T) (description) which is housed in an ST-connectorised synthetic package containing an InGaAs photodiode and Si bipolar transimpedance amplifier with a typical bandwidth of 125 MHz. Lower-cost alternatives are being evaluated for use in the final systems. A potential candidate is the TrueLight TRR-1B43-000 (description) photodiode+preamplifier, which is much less expensive. This device has a CMOS preamplifier with AGC, greatly extending the dynamic range. Although the 1B43 is physically similar to the 2316, note that it is not pin-compatible (in particular, the power supply polarity is reversed).
Since conventional optical single-fibre connectors and optoelectronic receivers are relatively bulky, a subminiature optical fibre connector and active device mount have been developed for special applications which allow timing receivers to be much smaller than telecommunications components. This "RD12" connector, which is now produced industrially by Lemo SA, has very low mass and is made from radiation-hard materials so that it may be appropriate for use within particle detectors. It is being evaluated for possible use in the CMS inner tracker. A subminiature connector-connector coupling bush has also been developed and this is being offered as an alternative to fibre splicing.
The RD12
connector has successfully undergone qualification tests specified by Boeing
for airborne applications. The manufacturer
should be contacted directly for further information.
Definition of DCS part:
Our baseline for now is the Altera with
embedded ARM core (EPXA1
in 484
FBGA
package). This is supposed to be quite
cheap in volume. This device I prefer
over the
NIOS type devices as first the FLASH and SDRAM interface has to be
programmed in the FPGA and it does not implement a cache
and thus DRAM is
very slow. SRAM is much more
expensive.
- Our general optimization strategy shall be lowest
possible cost (lowest
number of components) at
highest possible packing density (cost first, size
second). The unit shall receive external supply voltage (assume
poorly
regulated ~6V) and generates its required
internal voltages via regulators.
Voltages
needed on the board: 3.3, 1.8 for DCS
For TTCrx
: Absolute min/max values for VDD : 3.3-5.0 V ± 10 %
- minimum required FLASH and
Memory size
Currently the OS
consumes ~500kByte of Flash, the program (ROMDISK) 2.5Mbyte
- no serial FLASH ROM if at all possible. We shall
configure it
with specific FPGA
configuration through JTAG.
(Note from Tobias: ARM is
configurable like APEX: JTAG, passiv serial, parallel. I'd prefer usingan CPLD
config Controller, extendable to also rewrite the flash-rom (should be
possible). For configuration is another
possibility: the "boot-from-flash" option,- little
bit similar to configure with CPLD like on NIOS
dev. board. But here the ARM-CPU does config. It
starts up, reading out a boot-program locate
at 0x0 in attached flash ROM, which can configure
the device (In ARM-based devices is not) only the logic configured, also the
timing of SDRAM controller, Timer, CPU-behaviour, e.g. enable cache, cache
strategy etc.) In both cases we need possibility to change flash contents
externaly.)
Here is the note about ARM device booting
- FLASH / SDRAM bus width
SDRAM Controller (in ARM-stripe): EPXA1 in 484BGA does
only have 16Bit data bus. Greater
ones have the
option of 16 or 32 Bit. The biggest Device (EPXA10) has the only possibility:
32Bit.
SRAM/Flash Controller is connected to EBI
(Expansion Bus Interface) and has
16Bit data bus
(8 Bit configurable), Maximum Address width is 25 -> 32MB.
- FPGA pin map
- no real time clock for UCLinux - we shall use NTP
- Ethernet physical layer shall be left undefined for now
until results from
Munster.
(Note from Tobias: Details of how many
wires/pins are needed for TDK PHY Chip will be provided
soon from Christian Brecht, I'd suggest reservating
some space for the transformer, so we
have for tests full compliant Physical layer.
Perhaps it can be socket-mounted for later
addition/changing. In Cologne we have a proto-board
for TDK Chip on which is a real huge transformer (10x7x25 mm³). )
- connector for RS232 (only pin row for debugging)
- no V24
transmitters.
- Preliminary list of signals
on DCS-TTCmezzanine <--> MB connector:
pin count
- 4 DCS link rings + Jtag to
MB 48
- 2x3 DC
voltage measurement
inputs V on input of Vreg
(bars) 6
- 8x3 voltage
reg control pins
each for group of 3
reg.s
24
-ground
pins
8
- TTC
pins
10 (32 for distribution on DCS board)
-
reserve
10
----------------------------------------------------
106 (128)
- There shold be also "Global" JTAG ring allowing
reconfiguration of lost controllers
Routing of readout tree and DCS for the
whole chamber
---------------------------------------------------------------------
Here are several routing options for readout tree and DCS .
Aim is to
keep minimum # of mother-board designs. In this example
everything can be
done with one board design. Of coarse in such a case
quite a lot of
redundant lines have to be used.
This is ment mostly as basis for discussion with Ivan
Low drop Voltage regulators :
---------------------------------
Texas
Instruments: TPS70151 ,
TPS73HD318
,
STMicroelectronics: KF00 series , LFxx Series , overview of LD regulatros ,
National Semiconductors : LP2989LV , LP2992 ,
TPC approach:
TPC FEE. I can anticipate you that we are looking for a
rather
wide variety of LDOs, including RAD-HARD LDOs.
However, for the
time being in the FEC prototype we are
using COTS LDOS:
MICREL 39151_2.5BU
- 2.5V fixed voltage
- 1.5A
MICROCHIP TC1265_2.5
- 2.5V fixed voltage
- 800 mA
MICROCHIP TC1265_3.3
- 3.3V fixed voltage
- 800 mA
They all have the shutdown (on/off pin) and latchup
(overcurrent +
input undervlotage + high temperature
protection) features.
Moreover on the board we have a
circuit, upstream the LDOs, based on
discrete
transistors, to shutdown the board.
by Luciano Musa
Other usefull links:
------------------------
Component suppliers : AVX (passive components) , Samtec (connectors)
Component search > Chip directory , ChipDocs - the online datasheet source ,
