Ruprecht Karls Universität Heidelberg



Development of a test bench for the Pattern Recognition Engine

The High-Luminosity LHC will be the most challenging environment to perform online particle track reconstruction in the world. The ATLAS experiment addresses this challenge using pattern recognition fully implemented in hardware using several thousands of custom-designed Associative Memory ASICs (Application-Specific Integrated Circuit), which have an individual comparison power of 3.75 Petabyte per second per chip. We want to build a test bench for the printed circuit board, the so-called Pattern Recognition Mezzanine, which hosts 20 of these ASICs and an extremely powerful FPGA (Field-Programmable Gate Array). We offer bachelor and master theses. If interested please contact S.Dittmeier or A.Schöning.

Kontakt: Sebastian Dittmeier, André Schöning

Veröffentlicht am: 2020-07-10
EDV Abteilung