Minutes of the Electronics Meeting 5/6 Feb 2004 ------------------------------------------------ by U.U. Present: T.Sluijk, A.Zwart, A.Berkien, A.Pellegrino, M.Nedos, B.Spaan, R.Schwierz, L.Zimmermann, H.Deppe, U.Stange, U.Trunk, D.Wiedner, J.Knopf, U.Uwer 1. HV Boards: ------------- Tom summarized the status of the HV boards with encapsulated capacitors: Preseries I: problems at ~1% level. Sparking under caps. Preseries II: improved technology but broken caps, likely mechanical dammage. Preseries III: soldering company resoldered some caps manually which in consequence developed problems. Preseries iV: currently under way. We expect results by end of March. We need a decision on our baseline technology before the Electronics Review: an alternative is the potting of the caps under vaccuum. This technology also implies risks which must be studied. 2. ASD/OTIS Boards: ------------------- Albert presented the results he got testing the first assembled front-end box. GOL/Aux board: He added LVDS drivers for the clock distribution (necessary to allow good clock termination on the OTIS boards) -> see also Dirk's report. To damp the oscillations of the negative LV regulators 100 muF tantals capacitors have been added. OTIS board: Clock signals had to be terminated on the board. The PCB layer which was foreseen as heat conductor was produced by the manufacturer with a thickness of 35 mum instead the foreseen 100 mum. The LVDS receivers used on the OTIS boards uses +3V (also used for the ASDs) and causes noise on the ASDs (clock pickup). ASDBLR boad: The noise decreased from 35% to 1.8% if the negative inputs are left open (threshold 550 mV). As noise estimate the noise occupancy were given: 2% at 3 fC threshold 0% at 4.5 fC (150 evts taken) It was mentionned that these "noise" levels are quiet high for a test in the laboratory and that the noise will increase if a module is connected to the inputs. A good result is the low cross talk value measured: the analog cross talk between neighbouring channels (Board + chip) is determined to be ~1%. Power Consumtption: The following currents have been measured operating the full electronics box: 2.6 A at +5.3V 0.9 A at -5.3V => 18.5 W (agrees with our estimate) 3. GOL/Aus Board: ----------------- Dirk presented the test results of the first GOL/Aux board: - Oscillations of the neg. LV regulators can be treated by adding the 22 muF tantal capacitor: osc. amplitued only 24mV. - The clock signal after the QPLL have been shown. The rise time seemed to be slow. The effect on the OTIS resolution has to be studied. - The data transmission was tested with the card: a bit error rate of 10^-11 (instead of the former 10^-15) was obtained. The believe is that the cable used for the connection to the OTIS board is the suspicious. - for the clock distribution a passive LVDS distribution with current splitting is proposed. According to Dirk good signal quality can be obtained with only resistors. If this scheme is used a possible resolution dgradation of OTIS has to be studied. - for the next GOL/Aux board version a few changes are proposed: + new VCSEL diode (Ulm-Photonics) + decoupling of the I2C bus from the module: either by opto-couplers or by a passive components. Tome remarked the opto-couplers are either to slow or not rad-hard. 4. Thermal tests of the electronics box: ---------------------------------------- Ad summarized the the thermal testsdone with the fist proto-typ of the elctronics box. The complete box was insulated and operated. The baseplate was cooled by a raditor in air. After a warm-up time of 2h the temperature stablizes at the following values: at OTIS: 52 deg C at ASD: 42 deg at baseplate: 35 deg C This results is very encouraging and shows that the cooling problem can be handled with the current box design. 5. OTIS: -------- Harald summarized the change of OTIS1.1 w/r to OTIS1.0. The user manual can be found in: http://wwwasic.kip.uni-heidelberg.de/lhcbot/secure/Specifications/ OTIS11-UserManual.pdf UserID: Otis Passwd: DriftTime The implementation of the 2nd readout mode was discussed. The present people all supported the proposed submission of OTIS1.2 (=OTIS1.1 + 2nd readout mode) in the May MPW Run. This assumes that there are no principal problems with OTIS 1.1 anymore and that OTIS1.1 could be the fallback if OTIS1.2 fails. 6. Service/Distribution Boxes: ------------------------------- - High voltage distribution: each module end: 2 HV connections run to the counting room. -> for one curtain: 2 x 9 x 4 = 72 lines x 12 curtains => 864 HV lines In the counting room 4 - 6 lines are grouped and connected to active HV channels. - Low voltage: per curtain the following currents are neeeded 130 A for +5V and 40 A for -5V -> ~ 1kW / curtaiin - Optical fibers: It was agreed that one 12 fiber ribbon cable is used for a single stereo layers. A splitter cable 1x12 -> 12x1 is used as interface at the patch panel and for the connection to the modules. - TFC distribution box: there is yet no prototype of this box. The TTC distribution will consist out of a master service box containing the TTCRx and the SPECS card and a slave service box which contain essentially only the LVDS drivers for the I2C and the TTC signals. There is also need to define the cable and the connectors used for the TTC signals and the additional monitoring signals. In a discussion we pointed out that it is essentially to have a prototype of the TFC distribution boxes for the fall test. If the full implementation is time crtitcal we could limit the first protoyp to only the TTC signals and forget the about slow control signals. (the box is essential to test the TTC signal distribution for a stereo layer). 7. Optical fibers: ----------------- Dirk summarized the LHCb discussion on the "commmon" LHCb readout fiber: several groups are going to use ribbon cables with 50/125 mum multimode fibers. Thats the baseline also for the OT. 8. O-RxCard: ------------ Dirk summarized the status and the first tests of the 12 fold optical receiver card which is developed to be used as digital data-input of the TELL1 board. 9. Readout test system: ----------------------- Mirko presented the readout system based on an ALTERA APEX FPGA evaluation card. The system receives optical data. Data is synchronized and stored in a buffer (l1 buffer emulation). It can be readout by a PC via the PCI interface. Currently he is working to include a 2nd OTIS into the readout. Jan Knopf presented the idea to use a similar card (ALTERA STRATIX FPAG) as readout system for a stereo layer and as environment to develope the OT L1 code. During the discussion the need of a written specification to define the data synchronization became obvious. -> to be done before the electronics review. After the general meeting there was a discussion between people from Heidelberg and from Dresden to synchronize their efforts. 10. Testpulse system: --------------------- The testpulse was dscussed. There is yet no worked-out proposal. After a longer discussion the need of signals with different pulse height abandoned: differences in the electronics sensitivity can be observed with a single pulse height and a threshold scan. For diagnostics the amplifiers which have deteriorated can be studied in the laboratory. The choosen amplitude of the tespulse should allow a threshold but the the amplitude should lie above the noise threshold (which could be for some channels as large as 5 fC) to allow a good T0 determnation with little slew time corrections. The proposition is a pulse of 10 to 15 fC. It was decided to have sparate testpulse signals for even and odd channels. To adjust the testpulse in time with respect to the TTC clock signals it is proposed to use a programmable delay chip (Delay25). The discussion was concluded with the need to have a write-up for the electronics review. 11. Grounding Shielding: ------------------------ Tom presented the ideas on grounding: + floating LV supplies in the counting house + floatting HV outputs: In the counting house the HV ground (cable shield) should be connected with diodes to the safety ground. At the chambers the shield needs a low-impedance connections to the chambere reference ground which at the same time is equal to the safety ground. + gas-pipes should be insulated + all other connections to the counting house are optical. + all modules are connected to tye chamber frame which serves as reference and safety ground. Also here, the discussion was concluded with the need of a write-up. 12. Power Supply: ----------------- Tom presented the 2 alternatives for low volatge supply: - our baseline solution with power supplies in the counting house. According to him, the cable will hardly fit into the cable schikane. Moreover the power cables will heat up in the core to about 80 deg C. These are the main reasons our baseline is not supported by the management, although until now the proposal was never really rejected. - the alternative proposed by the experiment is the WIENER MARATON system (see presentation on the web). A single power module can provide only 46 A. The system is radiation and magnetic field toleant. We stressed once more that unless we are pushed by the experiment our baseline is to have the supplies in the counting house and that we have no manpower to investigate the WIENER system. 13. Schedule: ------------- We envisage a system test ("station test") in fall 2004: To have the electroncis ready in mid November to install the modules on the test frame the design of the Version 2 of all electronics components has to be finalized latest at the end of August and to launch the pre-series production latest at the beginning of September!! The same electronics should be used in the bem test which is foreseen for the end of fall 2004. The final electronics production should be planned such that the first final boards flow-in September 2005 to allow the installation at the chambers.