module gates(A, B, C, D, Yor, Ynor, Yxor, Yxnor, Yand, Ynand, Ynot1, Ynot2, Yor4, Ybuf);
input A, B, C, D;
output Yor, Yor4, Ynor;
output Yxor, Yxnor;
output Yand, Ynand;
output Ynot1, Ynot2;
output Ybuf;
// simple gates
or (Yor, A, B);
or (Yor4, A, B, C, D);
and (Yand, A, B);
nand (Ynand, C, D);
nor (Ynor, D, C);
xor (Yxor, A, B);
not (Ynot1, Ynot2, C);
xnor (Yxnor, D, C);
buf (Ybuf, B);
endmodule