module dff_s_r(d, clk, aclr, aset, qfdcp, qfdp);
input d, clk, aset, aclr;
output qfdcp, qfdp;
reg qfdcp, qfdp;
always @(posedge clk or posedge aset)
begin
if (aset==1) qfdp <= 1;
else qfdp <= d;
end
always @(posedge clk or posedge aset or posedge aclr)
begin
if (aset==1) qfdcp <= 1;
else
if (aclr==1) qfdcp <= 0;
else qfdcp <= d;
end
endmodule