LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity sort8 is generic(Nbits : Natural := 6; Nidx : Natural := 2; pairs : Boolean := false; ipipe : Boolean := true; mpipe : Boolean := true; opipe : Boolean := true); port( clk : in std_logic; dat0i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat1i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat2i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat3i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat4i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat5i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat6i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat7i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat0o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat1o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat2o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat3o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat4o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat5o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat6o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat7o : out std_logic_vector(Nbits+Nidx-1 downto 0)); end sort8; architecture struct of sort8 is component sort4c is generic(Nbits : Natural := 8; Nidx : Natural := 2; pairs : Boolean := true; ipipe : Boolean := true; mpipe : Boolean := true; opipe : Boolean := true); port( clk : in std_logic; dat0i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat1i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat2i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat3i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat0o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat1o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat2o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat3o : out std_logic_vector(Nbits+Nidx-1 downto 0)); end component; component dff_array is generic (N : Natural := 4); port ( clk : in std_logic; d : in std_logic_vector(N-1 downto 0); q : out std_logic_vector(N-1 downto 0) ); end component; type dat_array is array(0 to 7) of std_logic_vector(Nbits+Nidx-1 downto 0); signal dat_s : dat_array; signal dat_m : dat_array; begin pairs1: if pairs generate dat_s(0) <= dat0i; dat_s(1) <= dat1i; dat_s(2) <= dat2i; dat_s(3) <= dat3i; dat_s(4) <= dat4i; dat_s(5) <= dat5i; dat_s(6) <= dat6i; dat_s(7) <= dat7i; end generate; pairs0: if not pairs generate is_u: sort4c generic map(Nbits => Nbits, Nidx => Nidx, ipipe => ipipe, pairs => false, mpipe => mpipe, opipe => true) port map( clk => clk, dat0i => dat0i, dat1i => dat1i, dat2i => dat2i, dat3i => dat3i, dat0o => dat_s(0), dat1o => dat_s(1), dat2o => dat_s(2), dat3o => dat_s(3)); is_d: sort4c generic map(Nbits => Nbits, Nidx => Nidx, ipipe => ipipe, pairs => false, mpipe => mpipe, opipe => true) port map( clk => clk, dat0i => dat4i, dat1i => dat5i, dat2i => dat6i, dat3i => dat7i, dat0o => dat_s(4), dat1o => dat_s(5), dat2o => dat_s(6), dat3o => dat_s(7)); end generate; ms_u: sort4c generic map(Nbits => Nbits, Nidx => Nidx, ipipe => ipipe and pairs, pairs => true, mpipe => false, opipe => true) port map( clk => clk, dat0i => dat_s(0), dat1i => dat_s(1), dat2i => dat_s(4), dat3i => dat_s(5), dat0o => dat_m(0), dat1o => dat_m(1), dat2o => dat_m(2), dat3o => dat_m(3)); ms_d: sort4c generic map(Nbits => Nbits, Nidx => Nidx, ipipe => ipipe and pairs, pairs => true, mpipe => false, opipe => true) port map( clk => clk, dat0i => dat_s(2), dat1i => dat_s(3), dat2i => dat_s(6), dat3i => dat_s(7), dat0o => dat_m(4), dat1o => dat_m(5), dat2o => dat_m(6), dat3o => dat_m(7)); os_m: sort4c generic map(Nbits => Nbits, Nidx => Nidx, ipipe => false, pairs => true, mpipe => false, opipe => opipe) port map( clk => clk, dat0i => dat_m(2), dat1i => dat_m(3), dat2i => dat_m(4), dat3i => dat_m(5), dat0o => dat2o, dat1o => dat3o, dat2o => dat4o, dat3o => dat5o); op1: if opipe generate or0: dff_array generic map(N => dat0o'length) port map( clk => clk, d => dat_m(0), q => dat0o); or1: dff_array generic map(N => dat1o'length) port map( clk => clk, d => dat_m(1), q => dat1o); or6: dff_array generic map(N => dat6o'length) port map( clk => clk, d => dat_m(6), q => dat6o); or7: dff_array generic map(N => dat7o'length) port map( clk => clk, d => dat_m(7), q => dat7o); end generate; op0: if not opipe generate dat0o <= dat_m(0); dat1o <= dat_m(1); dat6o <= dat_m(6); dat7o <= dat_m(7); end generate; end;