LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; entity sort4c is generic(Nbits : Natural := 8; Nidx : Natural := 2; pairs : Boolean := false; ipipe : Boolean := false; mpipe : Boolean := false; opipe : Boolean := false); port( clk : in std_logic; dat0i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat1i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat2i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat3i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat0o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat1o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat2o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat3o : out std_logic_vector(Nbits+Nidx-1 downto 0)); end sort4c; architecture struct of sort4c is component dff_array is generic (N : Natural := 4); port ( clk : in std_logic; d : in std_logic_vector(N-1 downto 0); q : out std_logic_vector(N-1 downto 0) ); end component; signal d0gt1 : std_logic; signal d1gt2 : std_logic; signal d2gt3 : std_logic; signal d3gt0 : std_logic; signal d0gt2 : std_logic; signal d1gt3 : std_logic; type mux_ctrl is array(0 to 3) of std_logic_vector(1 downto 0); signal mux : mux_ctrl; signal sel : std_logic_vector(5 downto 0); type dat_array is array(0 to 3) of std_logic_vector(Nbits+Nidx-1 downto 0); signal dat_s : dat_array; signal dat_m : dat_array; signal dat_q : dat_array; begin ip1: if ipipe generate ir0: dff_array generic map(N => dat0i'length) port map( clk => clk, d => dat0i, q => dat_s(0)); ir1: dff_array generic map(N => dat1i'length) port map( clk => clk, d => dat1i, q => dat_s(1)); ir2: dff_array generic map(N => dat2i'length) port map( clk => clk, d => dat2i, q => dat_s(2)); ir3: dff_array generic map(N => dat3i'length) port map( clk => clk, d => dat3i, q => dat_s(3)); end generate; nip1: if not ipipe generate dat_s(0) <= dat0i; dat_s(1) <= dat1i; dat_s(2) <= dat2i; dat_s(3) <= dat3i; end generate; pairs1: if pairs generate d0gt1 <= '1'; d2gt3 <= '1'; end generate; pairs0: if not pairs generate d0gt1 <= '1' when dat_s(0)(Nbits+Nidx-1 downto Nidx) > dat_s(1)(Nbits+Nidx-1 downto Nidx) else '0'; d2gt3 <= '1' when dat_s(2)(Nbits+Nidx-1 downto Nidx) > dat_s(3)(Nbits+Nidx-1 downto Nidx) else '0'; end generate; d1gt2 <= '1' when dat_s(1)(Nbits+Nidx-1 downto Nidx) > dat_s(2)(Nbits+Nidx-1 downto Nidx) else '0'; d3gt0 <= '1' when dat_s(3)(Nbits+Nidx-1 downto Nidx) > dat_s(0)(Nbits+Nidx-1 downto Nidx) else '0'; d0gt2 <= '1' when dat_s(0)(Nbits+Nidx-1 downto Nidx) > dat_s(2)(Nbits+Nidx-1 downto Nidx) else '0'; d1gt3 <= '1' when dat_s(1)(Nbits+Nidx-1 downto Nidx) > dat_s(3)(Nbits+Nidx-1 downto Nidx) else '0'; mp1: if mpipe generate mrgi: for i in 0 to 3 generate mri: dff_array generic map(N => dat0i'length) port map( clk => clk, d => dat_s(i), q => dat_m(i)); end generate; process(clk) begin if clk'event and clk='1' then sel <= d0gt1 & d1gt2 & d2gt3 & d3gt0 & d0gt2 & d1gt3; end if; end process; end generate; nmp1: if not mpipe generate dat_m <= dat_s; sel <= d0gt1 & d1gt2 & d2gt3 & d3gt0 & d0gt2 & d1gt3; end generate; -- this LUT was generated by a C++ program process(sel) begin case sel is when "000100" => mux(0) <= "11"; mux(1) <= "10"; mux(2) <= "01"; mux(3) <= "00"; when "001100" => mux(0) <= "10"; mux(1) <= "11"; mux(2) <= "01"; mux(3) <= "00"; when "010100" => mux(0) <= "11"; mux(1) <= "01"; mux(2) <= "10"; mux(3) <= "00"; when "001101" => mux(0) <= "10"; mux(1) <= "01"; mux(2) <= "11"; mux(3) <= "00"; when "010101" => mux(0) <= "01"; mux(1) <= "11"; mux(2) <= "10"; mux(3) <= "00"; when "011101" => mux(0) <= "01"; mux(1) <= "10"; mux(2) <= "11"; mux(3) <= "00"; when "100100" => mux(0) <= "11"; mux(1) <= "10"; mux(2) <= "00"; mux(3) <= "01"; when "101100" => mux(0) <= "10"; mux(1) <= "11"; mux(2) <= "00"; mux(3) <= "01"; when "010110" => mux(0) <= "11"; mux(1) <= "01"; mux(2) <= "00"; mux(3) <= "10"; when "001001" => mux(0) <= "10"; mux(1) <= "01"; mux(2) <= "00"; mux(3) <= "11"; when "010111" => mux(0) <= "01"; mux(1) <= "11"; mux(2) <= "00"; mux(3) <= "10"; when "011001" => mux(0) <= "01"; mux(1) <= "10"; mux(2) <= "00"; mux(3) <= "11"; when "100110" => mux(0) <= "11"; mux(1) <= "00"; mux(2) <= "10"; mux(3) <= "01"; when "101000" => mux(0) <= "10"; mux(1) <= "00"; mux(2) <= "11"; mux(3) <= "01"; when "110110" => mux(0) <= "11"; mux(1) <= "00"; mux(2) <= "01"; mux(3) <= "10"; when "101001" => mux(0) <= "10"; mux(1) <= "00"; mux(2) <= "01"; mux(3) <= "11"; when "010011" => mux(0) <= "01"; mux(1) <= "00"; mux(2) <= "11"; mux(3) <= "10"; when "011011" => mux(0) <= "01"; mux(1) <= "00"; mux(2) <= "10"; mux(3) <= "11"; when "100010" => mux(0) <= "00"; mux(1) <= "11"; mux(2) <= "10"; mux(3) <= "01"; when "101010" => mux(0) <= "00"; mux(1) <= "10"; mux(2) <= "11"; mux(3) <= "01"; when "110010" => mux(0) <= "00"; mux(1) <= "11"; mux(2) <= "01"; mux(3) <= "10"; when "101011" => mux(0) <= "00"; mux(1) <= "10"; mux(2) <= "01"; mux(3) <= "11"; when "110011" => mux(0) <= "00"; mux(1) <= "01"; mux(2) <= "11"; mux(3) <= "10"; when "111011" => mux(0) <= "00"; mux(1) <= "01"; mux(2) <= "10"; mux(3) <= "11"; when others => mux(0) <= "--"; mux(1) <= "--"; mux(2) <= "--"; mux(3) <= "--"; end case; end process; mxi: for i in 0 to 3 generate dat_q(i) <= dat_m(conv_integer(mux(i))); end generate; op1: if opipe generate or0: dff_array generic map(N => dat0o'length) port map( clk => clk, d => dat_q(0), q => dat0o); or1: dff_array generic map(N => dat1o'length) port map( clk => clk, d => dat_q(1), q => dat1o); or2: dff_array generic map(N => dat2o'length) port map( clk => clk, d => dat_q(2), q => dat2o); or3: dff_array generic map(N => dat3o'length) port map( clk => clk, d => dat_q(3), q => dat3o); end generate; nop1: if not opipe generate dat0o <= dat_q(0); dat1o <= dat_q(1); dat2o <= dat_q(2); dat3o <= dat_q(3); end generate; end;