LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity shift_reg_var is port ( clk : in std_logic; d : in std_logic; q : out std_logic); end shift_reg_var; architecture a of shift_reg_var is begin process(clk) variable a,b,c : std_logic; begin if clk'event and clk='1' then c := b; -- this is the b := a; -- correct a := d; -- order! end if; q <= c; end process; end;