LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity shift_reg is generic (del : Time := 10 ns); port ( clk : in std_logic; rst_n : in std_logic; en_n : in std_logic; d : in std_logic; q : out std_logic); end shift_reg; architecture a of shift_reg is signal a : std_logic;--:= 'X'; signal b : std_logic;--:= 'X'; signal c : std_logic;--:= 'X'; begin process(clk, rst_n) begin if rst_n = '0' then q <= '0'; a <= '0'; c <= '0'; b <= '0'; elsif clk'event and clk='1' then if en_n = '0' then q <= c after del; b <= a after del; a <= d after del; c <= b after del; end if; end if; end process; end;