LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity prior is
port (
IRQ : in std_logic_vector(3 downto 0);
IRQ_no : out std_logic_vector(1 downto 0);
valid : out std_logic);
end prior;
architecture a of prior is
signal irq_pro : std_logic_vector(1 downto 0);
signal irq_when : std_logic_vector(1 downto 0);
signal valid_pro : std_logic;
signal valid_when : std_logic;
begin
-- using a process
pripro: process(IRQ)
begin
valid_pro <= '1';
irq_pro <= "--";
if (IRQ(3) = '1') then irq_pro <= "11";
elsif (IRQ(2) = '1') then irq_pro <= "10";
elsif (IRQ(1) = '1') then irq_pro <= "01";
elsif (IRQ(0) = '1') then irq_pro <= "00";
else valid_pro <= '0';
end if;
end process ;
-- an other priority encoder:
irq_when <= "11" when IRQ(3) = '1' else
"10" when IRQ(2) = '1' else
"01" when IRQ(1) = '1' else
"00" when IRQ(0) = '1' else
"--";
valid_when <= IRQ(0) or IRQ(1) or IRQ(2) or IRQ(3);
-- only one of the two groups
-- IRQ_no <= irq_pro;
-- valid <= valid_pro;
IRQ_no <= irq_when;
valid <= valid_when;
end;