LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; entity numones is generic (N : Natural := 4); port ( a : in std_logic_vector(N-1 downto 0); c : out std_logic_vector( 3 downto 0) ); end numones; architecture a of numones is begin process(a) variable nones : Integer range 0 to a'length; begin nones := 0; for i in a'range loop if a(i)='1' then nones := nones + 1; end if; end loop; c <= conv_std_logic_vector(nones, c'length); end process; end;