LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity gate_vect is
generic (N : Natural := 4);
port (
a : in std_logic_vector(N-1 downto 0);
g : in std_logic;
y : out std_logic_vector(N-1 downto 0) );
end gate_vect;
architecture a of gate_vect is
signal tmp : std_logic_vector(a'range);
begin
-- Use only one of the four descriptions!!!
-- 1
tmp <= (others => g);
y <= a and tmp;
-- 2
gn: for i in a'range generate
y(i) <= a(i) and g;
end generate;
-- 3
y <= a when g='1' else (others => '0');
-- 4
process(a,g)
begin
if g='1' then y <= a;
else y <= (others => '0'); end if;
end process;
end;