LIBRARY IEEE;
use IEEE.std_logic_1164.all;
entity filt_short is
generic (N : Integer := 3);
port(
clk : in std_logic;
d : in std_logic;
q : out std_logic);
end filt_short;
architecture a of filt_short is
signal samples : std_logic_vector(N-1 downto 0);
constant samples1 : std_logic_vector(N-1 downto 0) := (others => '1');
constant samples0 : std_logic_vector(N-1 downto 0) := (others => '0');
signal all_high, all_low_n, q_i : std_logic;
begin
all_high <= '1' when samples=samples1 else '0';
all_low_n <= '0' when samples=samples0 else '1';
process(clk)
begin
if clk'event and clk='1' then
samples <= samples(N-2 downto 0) & d;
q_i <= (q_i or all_high) and all_low_n;
end if;
end process;
q <= q_i;
end;