LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity fadd_top is
port (
cin : in std_logic;
a : in std_logic;
b : in std_logic;
cout : out std_logic;
s : out std_logic);
end fadd_top;
architecture a of fadd_top is
-- component declarations
component xor3 is
port (a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
y : out std_logic);
end component;
component a2of3 is
port (a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
y : out std_logic);
end component;
begin
-- instantiate the components
sum: xor3
port map(
a0 => a,
a1 => b,
a2 => cin,
y => s);
-- the recommended way
carr: a2of3
port map(
a0 => a,
a1 => cin,
a2 => b,
y => cout);
-- the shorter way, not recommended!
--carr: a2of3
--port map(a, cin, b, cout);
end;