LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.all; --USE IEEE.STD_LOGIC_UNSIGNED.all; entity adder is generic (N : Natural := 8; t_co : Time := 10 ns); port ( cin : in std_logic; a : in std_logic_vector(N-1 downto 0); b : in std_logic_vector(N-1 downto 0); cout : out std_logic; y : out std_logic_vector(N-1 downto 0) ); end adder; architecture a of adder is --signal sum : std_logic_vector(N downto 0); signal sum : unsigned(N downto 0); begin -- sum <= cin + ('0' & a) + ('0' & b); -- y <= sum(y'range); sum <= cin + unsigned('0' & a) + unsigned('0' & b); y <= std_logic_vector(sum(y'range)); cout <= sum(sum'high); end;