############### # X I L I N X # ############### # The location of the Xilinx simulation models xil_sim=c:\Xilinx\9.2\vhdl\src ############################# # Project specific settings # ############################# # The top level design name, used to derive some filenames design=cnt3 # The testbench file(s) testbench=./SRC/clk_gen.vhd ./SRC/$(design)_tb.vhd # XILINX post synthesis simulation # netlist after synthesis, usually at <project>/netgen/synthesis net_synx=../xilinx/netgen/synthesis/$(design)_synthesis.vhd # Xilinx post place & route simulation # netlist after place & route, usually at <project>/netgen/par net_parx=../xilinx/netgen/par/$(design)_timesim.vhd # sdf filename, usually in the same directory with the _timesim.vhd file sdf_xil=../xilinx/netgen/par/$(design)_timesim.sdf # The Xilinx unisim library unisim: vlib $@ vcom -quiet -93 -work $@ "$(xil_sim)\unisims\unisim_VPKG.vhd" vcom -quiet -93 -work $@ "$(xil_sim)\unisims\unisim_VCOMP.vhd" vcom -quiet -93 -work $@ "$(xil_sim)\unisims\unisim_SMODEL.vhd" vcom -quiet -93 -work $@ "$(xil_sim)\unisims\unisim_VITAL.vhd" # The Xilinx simprim library simprim: vlib $@ vcom -quiet -93 -work $@ "$(xil_sim)\simprims\simprim_Vpackage_mti.vhd" vcom -quiet -93 -work $@ "$(xil_sim)\simprims\simprim_Vcomponents_mti.vhd" vcom -quiet -93 -work $@ "$(xil_sim)\simprims\simprim_SMODEL_mti.vhd" vcom -quiet -93 -work $@ "$(xil_sim)\simprims\simprim_VITAL_mti.vhd" # Compile the synthesis netlist synthesisx: unisim $(net_synx) vlib $@ vcom -quiet -93 -work $@ $(net_synx) # Compile the p & r netlist layoutx: simprim $(net_parx) vlib $@ vcom -quiet -93 -work $@ $(net_parx) # Simulate the synthesis netlist simsyn: $(testbench) synthesisx vmap libdut synthesisx rm -rf work; vlib work vcom -quiet -93 -work work $(testbench) vsim 'work.$(design)_tb' -t 1ns -do 'wave_synx.do' # Simulate the p & r netlist without timing backannotation simlay: $(testbench) layoutx vmap libdut layoutx rm -rf work; vlib work vcom -quiet -93 -work work $(testbench) vsim 'work.$(design)_tb' -t 1ns -do 'wave_sdfx.do' # Simulate the p & r netlist with timing backannotation simsdf: $(testbench) layoutx vmap libdut layoutx rm -rf work; vlib work vcom -quiet -93 -work work $(testbench) vsim 'work.$(design)_tb' -sdftyp /dut=$(sdf_xil) -t 1ps -do 'wave_sdfx.do' # Simulate the p & r netlist with timing backannotation but no timing checks simsdf_nc: $(testbench) layoutx vmap libdut layoutx rm -rf work; vlib work vcom -quiet -93 -work work $(testbench) vsim 'work.$(design)_tb' +notimingchecks -sdftyp /dut=$(sdf_xil) -t 1ps -do 'wave_sdfx.do' # Clean all library directories clean: rm -rf work modelsim.ini transcript vsim.wlf simprim unisim synthesisx layoutx .PHONY: simsyn simlay simsdf simsdf_nc clean