############### # A L T E R A # ############### # The location of the Altera simulation models alt_sim=d:\Programme\q81\quartus\eda\sim_lib # Note that the family depends on the chip used in the project! alt_family=flex10ke alt_lib=$(alt_family)_components ############################# # Project specific settings # ############################# # The top level design name, used to derive some filenames design=cnt3 # The testbench file(s) testbench=./SRC/clk_gen.vhd ./SRC/$(design)_tb.vhd # ALTERA post place & route simulation net_para=../altera/simulation/modelsim/$(design).vho sdf_alt=../altera/simulation/modelsim/$(design)_vhd.sdo $(alt_lib): vlib $@ vcom -quiet -93 -work $@ "$(alt_sim)\$(alt_family)_atoms.vhd" vcom -quiet -93 -work $@ "$(alt_sim)\$(alt_family)_components.vhd" vmap $(alt_family) $@ layouta: $(alt_lib) $(net_para) vlib $@ vcom -quiet -93 -work $@ $(net_para) # Simulate the p & r netlist without timing backannotation simlay: $(testbench) layouta vmap libdut layouta rm -rf work; vlib work vcom -quiet -93 -work work $(testbench) vsim 'work.$(design)_tb' -t 1ns -do 'wave_sdfa.do' # Simulate the p & r netlist with timing backannotation simsdf: $(testbench) layouta vmap libdut layouta rm -rf work; vlib work vcom -quiet -93 -work work $(testbench) vsim 'work.$(design)_tb' -sdftyp /dut=$(sdf_alt) -t 1ps -do 'wave_sdfa.do' # Clean all library directories clean: rm -rf functional work modelsim.ini transcript vsim.wlf $(alt_lib) layouta .PHONY: simlay simsdf clean