Previous Project

The Hardware Tracking for the Trigger System (HTT)

The HTT system was planned to be a dedicated custom hardware sytem able to reconstruct tracks of charged particles in the ATLAS ITk detector at 1 MHz with low latency. It was meant to be part of the Event Filter system for the ATLAS TDAQ upgrade at the High-Luminosity LHC, reducing the computational load on the CPUs. Its low latency design, which followed the general approach from the ATLAS Fast TracKer (FTK) project, would have furthermore allowed for the usage as dedicated Level-1 hardware trigger, sustaining L0 trigger rates of up to 4 MHz. This would have allowed to lower pT-thresholds in the Level-0 hardware trigger and thus enhance the physics sensitivity of ATLAS.

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Baseline scenario of the TDAQ Phase II Upgrade, including HTT as co-processor in the Event Filter [TDR].

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So called evolved TDAQ architecture, with regional tracking of HTT being promoted to a hardware trigger level (L1Track), and global tracking remaining in the Event Filter (gHTT) [TDR].


The HTT would have been composed of about 700 ATCA boards, based on powerful FPGAs for communication and data processing, and custom-designed Associative Memory ASICs for pattern matching of incoming detector data with pre-computed track patterns derived from simulations.
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HTT is divided into independent units, consisting of 12 Associate Memory Tracking Processors (AMTP) ATCA boards (TP + PRM) and 2 Second Stage Tracking Processors (SSTP) ATCA boards (TP + 2 TFM), that are communicating with the network via dedicated HTT-Interface (HTTIF) cards [TDR].

Our contributions

Our group was mainly involved in the development of the Pattern Recongition Mezzanine (PRM), as well as in the development of the Associative Memory ASIC (AM ASIC, version AM 08).

The PRM is the key part of the HTT system, hosting 20 AM ASICs and 1 powerful FPGA (Intel Stratix 10 MX). Here, the pattern matching step, as well as a linearized track fit take place. The design takes advantage of the High-Bandwidth Memory included in the Intel Stratix 10 MX, which offers 8 GByte of DRAM without requiring any external interfaces on the PCB. Within the HBM, the pattern database stored in the AM ASICs is mirrored, and all constansts needed by the track fit track parameter estimation algorithms can be stored and retrieved quickly.
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Demonstrator PRM board with Intel Stratix 10 MX mounted and in operation.
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PRM firmware diagram [PRM].

We have substantially contributed to the development of the PRM firmware, in particular to the track fit, and the interfaces to the High-Bandwidth Memory and the AM ASICs.

We have also contributed to the development of the AM 08 - to its digital design and to the testing. We have developed a probe socket with PTSL that allows us to probe the bare dies before they were packaged. This allowed us to speed up the verification of AM ASIC's functionality.
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AM 08 bare dies inside a waffle pack.
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Probe card developed with PTSL to test the bare AM 08 dies.

In 2021, the HTT project has been cancelled by the ATLAS collaboration. Performance studies of L1Track have been conducted using fast emulation. The results are summarized in a PUB-note.
"Performance studies of tracking-based triggering using a fast emulation"
The ATLAS Collaboration
ATL-DAQ-PUB-2023-001